1. Field of the Invention
Embodiments of the present invention generally relate to methods for forming semiconductor devices. More particularly, embodiments of the present invention generally relate to methods for etching an etching stop layer disposed on a substrate using a cyclically etching process for manufacturing semiconductor devices.
2. Description of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technology challenges for next generation very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of circuit technology are pushed, the shrinking dimensions of VLSI and ULSI interconnect technology have placed additional demands on processing capabilities. Reliable formation of gate structures on the substrate is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
A patterned mask, such as a photoresist layer, is commonly used in forming structures, such as gate structure, shallow trench isolation (STI), bit lines and the like, on a substrate by an etching process. The patterned mask is conventionally fabricated by using a lithographic process to optically transfer a pattern having the desired critical dimensions to a layer of photoresist. The photoresist layer is then developed to remove undesired portion of the photoresist, thereby creating openings in the remaining photoresist.
In order to enable fabrication of next generation devices and structures, the geometry limits of the structures designed to be formed for the semiconductor devices has been pushed against technology limits, the need for accurate process control for the manufacture of small critical dimensional structures with high aspect ratio has become increasingly important. Poor process control during etching process will result in irregular structure profiles and line edge roughness, thereby resulting in poor line integrity of the formed structures. Additionally, irregular profiles and growth of the etching by-products formed during etching may gradually block the small openings used to fabricate the small critical dimension structures, thereby resulting in bowed, distorted, toppled, or twisted profiles of the etched structures.
Furthermore, the similarity between the materials selected for the hardmask layer, the adjacent layers and the underlying etching stop layer disposed in the film stack, and even the underlying material on the substrate, may also result in similar etch properties therebetween, thereby resulting in poor selectivity during etching. Poor selectivity between the hardmask layer, adjacent layers and the materials on the substrate may result in non-uniform, tapered and deformed profile of the hardmask layer, thereby leading to poor pattern transfer and failure of accurate structure dimension control. Accordingly, the etching stop layer is often utilized to provide an etching stop interface that may provide a high etching selectivity to assist protecting the underlying materials from damage and reduce likelihood of over-etching.
Thus, the chemical etchant used in the etch process is required to have a greater etch selectivity for the adjacent material layers, the etching stop layer and the underlying upper surface of the material layer, either a conductive layer or a dielectric layer, so as to provide a good interface control. When the etching stop layer is etched, the adjacent material layers may be attacked by the reactive etchant species, resulting in non-uniformity or tapered profile on the top and/or sidewall of the adjacent material layers, resulting in undesired profile deformation. Thus, a highly selective etchant enhances for accurate pattern transfer is desired. However, conventional etchants are not selective enough to enable robust manufacturing of next generation devices.
Thus, there is a need for improved methods for etching an etching stop layer for manufacturing semiconductor devices with high selectivity and accurate process and profile control.